Sat
May
23
VLSI
Bit-Sliced CPU8
Part I. Register Decoder*******************
1.INV:
http://shygofish.myweb.hinet.net/slides/inv.html



2.NAND2:
http://shygofish.myweb.hinet.net/slides/nand2.html



3.EN_CELL:1bit編碼器
http://shygofish.myweb.hinet.net/slides/en_cell.html



4.DE_CELL:
http://shygofish.myweb.hinet.net/slides/de_cell.html



5.Decoder:8bit解碼器
http://shygofish.myweb.hinet.net/slides/decoder.html



Part II Register File************************
6.Register:
http://shygofish.myweb.hinet.net/slides/reg_cell.html

7.8x8 register:
http://shygofish.myweb.hinet.net/slides/reg8x8.html

Part III Control Unit*******************
8.Control Unit:
http://shygofish.myweb.hinet.net/slides/op_cntl.html
9.nand4:


10.tinv: Tristate inverter
http://shygofish.myweb.hinet.net/slides/tinv.html



Part Ⅳ Logic Unit********************
11.1-bit logic:
http://shygofish.myweb.hinet.net/slides/logic.html

12.8-bit logic:
http://shygofish.myweb.hinet.net/slides/logic8.html
Part Ⅴ Arithematic Unit*******************
13.Full Adder:
http://shygofish.myweb.hinet.net/slides/fadd.html

14.2-to-1 multiplexer:
http://shygofish.myweb.hinet.net/slides/mux2.html

15.oparith:
http://shygofish.myweb.hinet.net/slides/oparith.html

16.1-bit Arithematic:
http://shygofish.myweb.hinet.net/slides/arithematic.html

17.8-bits Arithematic:
http://shygofish.myweb.hinet.net/slides/arithematic8.html

Part Ⅵ Top of bit-sliced ********************
18.Top:cpu-8bit?
http://shygofish.myweb.hinet.net/slides/cpu8.html